Altera Arria V Avalon-MM User Manual
Page 85
Byte Offset
Register
Dir
Description
14'h3C08
cfg_link_ctrl[15:0]
O
cfg_link_ctrl[15:0]
is the primary Link Control
of the PCI Express capability structure.
For Gen2 or Gen3 operation, you must write a 1’b1
to Retrain Link bit (Bit[5] of the
cfg_link_ctrl)
of
the Root Port to initiate retraining to a higher data
rate after the initial link training to Gen1 L0 state.
Retraining directs the LTSSM to the Recovery state.
Retraining to a higher data rate is not automatic for
the Arria V Hard IP for PCI Express IP Core even if
both devices on the link are capable of a higher data
rate.
14'h3C0C
cfg_link_ctrl2[15:0]
O
cfg_link_ctrl2[31:16]
is the secondary Link
Control register of the PCI Express capability
structure for Gen2 operation.
When
tl_cfg_addr=2
,
tl_cfg_ctl
returns the
primary and secondary Link Control registers,
{cfg_link_ctrl[15:0], cfg_link_
ctrl2[15:0]}
, the primary Link Status register
contents is available on
tl_cfg_sts[46:31]
.
For Gen1 variants, the link bandwidth notification
bit is always set to 0. For Gen2 variants, this bit is
set to 1.
14'h3C10
cfg_prm_cmd[15:0]
O
Base/Primary Command register for the PCI
Configuration Space.
14'h3C14
cfg_root_ctrl[7:0]
O
Root control and status register of the PCI-Express
capability. This register is only available in Root
Port mode.
14'h3C18
cfg_sec_ctrl[15:0]
O
Secondary bus Control and Status register of the
PCI-Express capability. This register is only
available in Root Port mode.
14'h3C1C
cfg_secbus[7:0]
O
Secondary bus number. Available in Root Port
mode.
14'h3C20
cfg_subbus[7:0]
O
Subordinate bus number. Available in Root Port
mode.
14'h3C24
cfg_msi_addr_low[31:0]
O
cfg_msi_add[31:0]
is the MSI message address.
UG-01105_avmm
2014.12.15
Control Register Access (CRA) Avalon-MM Slave Port
5-23
Registers
Altera Corporation