Altera Arria V Avalon-MM - Manual (Page 161)

Date Version Changes Made
• Added figure showing connectivity for the Transceiver Reconfigu‐
ration Controller and Altera PCIe Reconfig Driver IP Cores to the
Gettting Started chapter.
• Removed Maximum and High settings from the RX Buffer credit
allocation -performance for received requests setting. These
settings are not available for the Avalon-MM interface and could
lead to data corruption.
• Revised Receiving a Completion TLP under Programming Model
for Avalon-MM Root Port to cover read and non-posted
completions.
2014.06.30 14.0
Added the following features to the Arria V Avalon-MM Hard IP for
PCI Express:
• Added access to selected Configuration Space registers and link
status registers through the optional Control Register Access
(CRA) Avalon-MM slave port.
• Added optional hard IP status bus that includes signals necessary
to connect the Transceiver Reconfiguration Controller IP Core.
• Added optional hard IP status extension bus which includes
signals that are useful for debugging, including: link training,
status, error, and Configuration Space signals.
• For
TxsByteEnable_i[-1:0]
, added restrictions on the legal
patterns of enabled and disabled bytes.
• Clarified the behavior of the
TxsWaitrequest_o
signal.
Made the following changes to the user guide:
• Created separate user guides for variants using the Avalon-MM,
Avalon-ST, and Avalon-MM with DMA interfaces to the Applica‐
tion Layer.
• Corrected frequency range for
hip_reconfig_clk
. It should be
100-125 MHz.
• Simplified the Getting Started chapter. It copies the Gen1 x4
example from the install directory and does not include step-by-
step instructions to recreate the design.
• Added Next Steps in Creating a Design for PCI Express to
Datasheet chapter.
• Removed references to the MegaWizard ® Plug-In Manager. In
14.0 the IP Parameter Editor Powered by Qsys has replaced the
MegaWizard Plug-In Manager.
• Added definition for
test_in[6]
and link to Knowledge Base
Solution on observing the PIPE interface signals on the
test_out
bus.
C-2 Revision History for the Avalon-MM Interface
UG-01105_avmm
2014.08.18
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