Control register access (cra) avalon-mm slave port – Altera Arria V Avalon-MM User Manual
Page 84
The
PCI Express-to-Avalon-MM Mailbox
registers are read-only at the addresses shown in the
following table. The Avalon-MM processor reads these registers when the corresponding bit in the
PCI
Express to Avalon-MM Interrupt Status
register is set to 1.
Table 5-22: PCI Express to Avalon-MM Mailbox Registers, 0x3B00–0x3B1F
Address
Name
Access
Mode
Description
0x3B00
P2A_MAILBOX0
RO
PCI Express-to-Avalon-MM mailbox 0
0x3B04
P2A_MAILBOX1
RO
PCI Express-to-Avalon-MM mailbox 1
0x3B08
P2A_MAILBOX2
RO
PCI Express-to-Avalon-MM mailbox 2
0x3B0C
P2A_MAILBOX3
RO
PCI Express-to-Avalon-MM mailbox 3
0x3B10
P2A_MAILBOX4
RO
PCI Express-to-Avalon-MM mailbox 4
0x3B14
P2A_MAILBOX5
RO
PCI Express-to-Avalon-MM mailbox 5
0x3B18
P2A_MAILBOX6
RO
PCI Express-to-Avalon-MM mailbox 6
0x3B1C
P2A_MAILBOX7
RO
PCI Express-to-Avalon-MM mailbox 7
Control Register Access (CRA) Avalon-MM Slave Port
Table 5-23: Configuration Space Register Descriptions
For registers that are less than 32 bits, the upper bits are unused.
Byte Offset
Register
Dir
Description
14'h3C00
cfg_dev_ctrl[15:0]
O
cfg_devctrl[15:0]
is device control for the PCI
Express capability structure.
14'h3C04
cfg_dev_ctrl2[15:0]
O
cfg_dev2ctrl[15:0]
is device control 2 for the
PCI Express capability structure.
5-22
Control Register Access (CRA) Avalon-MM Slave Port
UG-01105_avmm
2014.12.15
Altera Corporation
Registers