C. additional information, Revision history for the avalon-mm interface, Additional information – Altera Arria V Avalon-MM User Manual
Page 160
Additional Information
C
2014.08.18
UG-01105_avmm
Revision History for the Avalon-MM Interface
Date
Version
Changes Made
2014.12.15
14.1
Made the following changes to the user guide:
• In the figured titled Specifying the Number of Transceiver
Interfaces for Arria V and Cyclone V Devices, removed the
Calibrate duty cycle during power up. Duty cycle calibration
occurs during Gen1 to Gen2 speed changes. This is no longer a
parameter than you can turn on and off.
• Corrected discussion of soft and hard reset controllers. The
hardened reset controller is used for Arria V and Cyclone V
devices.
• Added statement that the bottom left hard IP block includes the
CvP functionality for flip chip packages. For other package types,
the CvP functionality is in the bottom right block.
• Corrected bit definitions for
CvP Status
register.
• Updated definition of
CVP_NUMCLKS
in the
CvP Mode Control
register.
• Added definitions for
test_in[2]
,
test_in[6]
and
test_in[7]
.
• Removed requirement that
TxsWrite_i
be asserted continuously
throughout a write burst.
TxsWrite_i
may be deasserted and
reasserted during a burst.
• Corrected Channel Utilization table for x1 instances. Data is
driven on Channel 0. The CMU clock is on Channel 1.
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