Altera Arria V Avalon-MM - Manual (Page 77)

Address Range Register
0x3070 INT-X Interrupt Enable Register for Root Ports
0x3070 INT-X Interrupt Enable Register for Endpoints
0x3A00-0x3A1F Avalon-MM to PCI Express Mailbox Registers
0x3B00-0x3B1F PCI Express to Avalon-MM Mailbox Registers
0x3C00-0x3C6C Host (Avalon-MM master) access to selected Configuration Space and status registers.
Avalon-MM to PCI Express Interrupt Registers
Avalon-MM to PCI Express Interrupt Status Registers
These registers contain the status of various signals in the PCI Express Avalon-MM bridge logic and allow
PCI Express interrupts to be asserted when enabled. Only Root Complexes should access these registers;
however, hardware does not prevent other Avalon-MM masters from accessing them.
Table 5-13: Avalon-MM to PCI Express Interrupt Status Register, 0x0040
Bit Name Access Description
[31:24] Reserved N/A N/A
[23] A2P_MAILBOX_INT7 RW1C 1 when the A2P_MAILBOX7 is written to
[22] A2P_MAILBOX_INT6 RW1C 1 when the A2P_MAILBOX6 is written to
[21] A2P_MAILBOX_INT5 RW1C 1 when the A2P_MAILBOX5 is written to
[20] A2P_MAILBOX_INT4 RW1C 1 when the A2P_MAILBOX4 is written to
[19] A2P_MAILBOX_INT3 RW1C 1 when the A2P_MAILBOX3 is written to
[18] A2P_MAILBOX_INT2 RW1C 1 when the A2P_MAILBOX2 is written to
[17] A2P_MAILBOX_INT1 RW1C 1 when the A2P_MAILBOX1 is written to
[16] A2P_MAILBOX_INT0 RW1C 1 when the A2P_MAILBOX0 is written to
UG-01105_avmm
2014.12.15
Avalon-MM to PCI Express Interrupt Registers 5-15
Registers Altera Corporation
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