Digilent 6003-410-000P-KIT User Manual
Page 63
XUP Virtex-II Pro Development System
63
UG069 (v1.0) March 8, 2005
Using the Fast Ethernet Network Interface
R
The Ethernet network interface is made up of three distinct components: the Media Access
Controller (MAC) contained in the FPGA, a physical layer transceiver (PHY), and the
Ethernet coupling magnetics.
The LXT972A (U12) is an IEEE 802.3-compliant Fast Ethernet physical layer (PHY)
transceiver that supports both 100BASE-TX and 10BASE-T operation. It provides the
standard Media Independent Interface (MII) for easy attachment to 10/100 (MACs). The
LXT972A supports full-duplex operation at 10 Mb/s and 100 Mb/s. The operational mode
can be set using auto-negotiation, parallel detection, or manual control.
The LXT972A performs all functions of the physical coding sublayer (PCS), the physical
media attachment (PMA) sublayer, and the physical media dependent (PMD) sublayer for
100BASE-TX connections.
The LXT972A reads its three configuration pins on power up to check for forced operation
settings. If it is not configured for forced operation at 10 Mb/s or 100 Mb/s, the device uses
auto-negotiation/parallel detection to automatically determine line operating conditions.
If the PHY on the other end of the link supports auto-negotiation, the LXT972A auto-
negotiates with it, using fast link pulse (FLP) bursts. If the other PHY does not support
auto-negotiation, the LXT972A automatically detects the presence of either link pulses
(10BASE-T) or idle symbols (100BASE-TX) and sets its operating mode accordingly.
The LXT972A configuration pins are set to allow for auto-negotiation, 10 Mb/s or
100 Mb/s, full-duplex or half-duplex operation. These settings can be overridden by
setting control bits in the Media Independent Interface (MII) registers.
The slew rate of the transmitter outputs is controlled by the two slew control inputs. It is
recommended that the slowest slew rate be set by driving both of the slew inputs with a
logical 1.
Three LEDs are available to provide visual status information about the Ethernet link
connection. If a link has been established, the LINK UP LED is turned on. If the link is a
100 Mb/s link, then the SPEED LED also turns on. The RX_DATA LED blinks, indicating
that packets are being received. Setting control bits in the MII registers can alter the
function of the three LEDs.
The LX972A provides the interface to the physical media; the MAC resides in the FPGA
and is available as an IP core.
The 10/100 Ethernet requires transformer coupling between the PHY and the RJ-45
connector to provide electrical protection to the system. The magnetics used on the XUP
Virtex-II Pro Development System are integrated into the RJ45 connector (J10) from the
FastJack
™ series of connectors from Halo Electronics, Inc. The HFJ11-2450 provides a
significant real estate reduction over non-integrated solutions.
identifies the
connections between the FPGA and the PHY.
The type of network cable that is used with the XUP Virtex-II Pro Development System
depends on how the system is connected to the network. If the XUP Virtex-II Pro
Development System is connected directly to a host computer, then a cross-over Ethernet
cable is required. However, if the system is connected to the network through a hub or
router, then a normal straight-through Ethernet cable is required.