Ddr sdram test, Additional hardware required, Test procedure – Digilent 6003-410-000P-KIT User Manual
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XUP Virtex-II Pro Development System
1-800-255-7778
UG069 (v1.0) March 8, 2005
Appendix D: Using the Golden FPGA Configuration for System Self-Test
R
DDR SDRAM Test
This test begins when “5” is selected from the BIST Main Menu. It first uses the serial detect
lines to determine if a DIMM module is seated in the memory slot. If one is identified, it
proceeds to read the configuration registers to determine if the module is currently
supported by the XUP Virtex-II Pro Development System.
The registers of interest include the following:
•
Register 2: memory type – only DDR memories (type = 7) are supported.
•
Register 3: row address count – only devices with 13 row addresses are supported.
•
Register 4: column address count – only devices with 10 column addresses are
supported.
•
Register 5: rank count – single and dual rank devices (rank count = 1 or 2) are
supported.
Once a valid memory device has been detected, the memory test begins. The complete
memory verification consists of the following tests:
•
Data bus walking 1’s test
•
Data bus walking 0’s test
•
Address bus walking 1’s test
•
Address bus walking 0’s test
•
Device pattern test – a counter value is written to each memory location then read
back
•
Device inverse pattern test – the inverse of the counter value is written to each
memory location then read back
Additional Hardware Required
•
A 64M x 64 or 64M x 72 dual rank DDR SDRAM module properly seated in the
memory slot
Test Procedure
1.
After the DDR SDRAM test is selected from the BIST Main Menu, the test begins
immediately with the serial presence detect. If a supported module is detected, the
complete memory verification begins for each available rank. The terminal window
output for the DDR SDRAM test is shown in
.