Digilent 6003-410-000P-KIT - Manual (Page 17)

XUP Virtex-II Pro Development System www.xilinx.com 17
UG069 (v1.0) March 8, 2005
General Description R
Multi-Gigabit Transceivers
Four of the eight Multi-Gigabit Transceivers (MGTs) that are present in the Virtex-II Pro
FPGA are brought out to connectors and can be utilized by the user. Three of the
bidirectional MGT channels are terminated at Serial Advanced Technology Attachment
(SATA) connectors and the fourth channel terminates at user-supplied Sub-Miniature A
(SMA) connectors. The MGT transceivers are equipped with a 75 MHz clock source that is
independent for the system clock to support standard SATA communication. An
additional MGT clock source is available through a differential user-supplied (SMA)
connector pair. Two of the ports with SATA connectors are configured as Host ports and
the third SATA port is configured as a Target port to allow for simple board-to-board
networking.
System RAM
The XUP Virtex-II Pro Development System has provision for the installation of user-
supplied JEDEC-standard 184-pin dual in-line Double Data Rate Synchronous Dynamic
RAM memory module. The board supports buffered and unbuffered memory modules
with a capacity of 2 GB or less in either 64-bit or 72-bit organizations. The 72-bit
organization should be used if ECC error detection and correction is required.
System ACE Compact Flash Controller
The System Advanced Configuration Environment (System ACE™) Controller manages
FPGA configuration data. The controller provides an intelligent interface between an
FPGA target chain and various supported configuration sources. The controller has several
ports: the Compact Flash port, the Configuration JTAG port, the Microprocessor (MPU)
port and the Test JTAG port. The XUP Virtex-II Pro Development System supports a single
System ACE Controller. The Configuration JTAG ports connect to the FPGA and front
expansion connectors. The Test JTAG port connects to the JTAG port header and USB2
interface CPLD, and the MPU ports connect directly to the FPGA.
Fast Ethernet Interface
The XUP Virtex-II Pro Development System provides an IEEE-compliant Fast Ethernet
transceiver that supports both 100BASE-TX and 10BASE-T applications. It supports full
duplex operation at 10 Mb/s and 100 Mb/s, with auto-negotiation and parallel detection.
The PHY provides a Media Independent Interface (MII) for attachment to the 10/100
Media Access Controller (MAC) implemented in the FPGA. Each board is equipped with a
Silicon Serial Number that uniquely identifies each board with a 48-bit serial number. This
serial number is retrieved using “1-Wire” protocol. This serial number can be used as the
system MAC address.
Serial Ports
The XUP Virtex-II Pro Development System provides three serial ports: a single RS-232
port and two PS/2 ports. The RS-232 port is configured as a DCE with hardware
handshake using a standard DB-9 serial connector. This connector is typically used for
communications with a host computer using a standard 9-pin serial cable connected to a
COM port. The two PS/2 ports could be used to attach a keyboard and mouse to the XUP
Virtex-II Pro Development System. All of the serial ports are equipped with level-shifting
circuits, because the Virtex-II Pro FPGAs cannot interface directly to the voltage levels
required by RS-232 or PS/2.