Digilent 6003-410-000P-KIT User Manual
Page 21
XUP Virtex-II Pro Development System
21
UG069 (v1.0) March 8, 2005
Configuring the FPGA
R
The Platform Flash is normally disabled after the FPGA is finished configuring and has
asserted the DONE signal. If additional data is made available to the FPGA after the
completion of configuration, jumper JP9 must be moved from the NORMAL to the
EXTENDED position to permanently enable the PROM and allow the FPGA to clock out
the additional data using the FPGA_PROM_CLOCK signal. The process of loading
additional non-configuration data into the FPGA is outlined in application note:
Reading User Data from Configuration PROMs.
If the CONFIG SOURCE switch is open, off, or down, a lower speed JTAG-based
configuration from Compact Flash or external JTAG source is selected as the configuration
source. This is identified to the user through the illumination of the JTAG CONFIG LED
(D20).
The JTAG-based configuration can originate from several sources: the Compact Flash card,
a PC4 cable connection through J27, and a USB to PC connection through J8 the embedded
Platform Cable USB interface.
If a JTAG-based configuration is selected, the default source is from the Compact Flash
port (J7). The System ACE controller checks the associated Compact Flash socket and
storage device for the existence of configuration data. If configuration data exists on the
storage device, the storage device becomes the source for the configuration data. The file
structure on the Compact Flash storage device supports up to eight different configuration
data files, selected by the triple CF CONFIG SELECT DIP switch (SW8). During JTAG
configuration, the SYSTEMACE STATUS LED (D12) flashes until the configuration process
is completed, and the FPGA asserts the FPGA_DONE signal and illuminates the DONE
LED (D4). At any time, the RESET_RELOAD pushbutton (SW1) can be used to load any of
the eight different configuration data files by pressing the switch for more than 2 seconds.
If a JTAG-based configuration is selected and a valid configuration file is not found on the
Compact Flash card by the System ACE controller (U2), the SYSTEMACE ERROR LED
(D11) flashes, and the System ACE controller connects to an external JTAG port for FPGA
configuration.
The default external source for FPGA configuration is the high-speed embedded Platform
Cable USB configuration port (J8) and is enabled when the System ACE controller does not
find configuration data on the storage device. Detailed instructions on using the high-
speed Platform Cable USB interface can be found in
Appendix A, “Configuring the FPGA
from the Embedded USB Configuration Port.”
If a USB-equipped host PC is not available as a configuration source, then a Parallel Cable
4 (PC4) interface can be used instead by connecting a PC4 cable to J27.
It should be noted that if SelectMap byte-wide configuration from the on-board Platform
Flash configuration PROM is enabled, the FPGA Start-Up Clock should be set to CCLK in
the Startup Options section of the Process Options for the generation of the programming
file, otherwise JTAG Clock should be selected.