Digilent 6003-410-000P-KIT - Manual (Page 35)

XUP Virtex-II Pro Development System www.xilinx.com 35
UG069 (v1.0) March 8, 2005
Using the XSGA Output R
Design files supplied by Xilinx generate the required timing signals
VGA_OUT_BLANK_Z, VGA_HSYNCH, VGA_VSYNCH, and VGA_COMP_SYNCH, as
well as memory addressing for bit- and character-mapped display RAM. Character-
mapped mode allows for the display of extended ASCII characters in an 8 x 8 pixel block
without having to draw the character pixel by pixel. Compile time parameters are passed
to the Verilog code that defines the XSGA controller operation. The 100 MHz clock is used
as a source for one of the DCMs to create the video clock. By setting appropriate M and D
values for the DCM, various VGA_OUT_PIXEL_CLOCK rates can be created.