Digilent 410-183P-KIT - Manual

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Basys3™ FPGA Board Reference Manual
Revised August 12, 2014
This manual applies to the Basys3 rev. C
Overview
The Basys3 board is a complete, ready-to-use digital circuit development platform based on the latest Artix®-7
Field Programmable Gate Array (FPGA) from Xilinx®. With its high-capacity FPGA (Xilinx part number XC7A35T-
1CPG236C),
low overall cost, and collection of USB, VGA, and other ports, the Basys3 can host designs ranging from
introductory combinational circuits to complex sequential circuits like embedded processors and controllers. It
includes enough switches, LEDs, and other I/O devices to allow a large number of designs to be completed without
the need for any additional hardware, and enough uncommitted FPGA I/O pins to allow designs to be expanded
using Digilent Pmods or other custom boards and circuits.
The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more
resources than earlier designs. Artix-7 35T features include:
The Basys3 also offers an improved collection of ports and peripherals, including:
• 16 user switches • 16 user LEDs • 5 user pushbuttons
• 4-digit 7-segment display • Three Pmod connectors • Pmod for XADC signals
• 12-bit VGA output • USB-UART Bridge • Serial Flash
• Digilent USB-JTAG port for
FPGA programming and
communication
• USB HID Host for mice, keyboards
and memory sticks
The Basys3 works with Xilinx’s new high-performance Vivado™ Design Suite. Vivado includes many new tools and
design flows that facilitate and enhance the latest design methods. It runs faster, allows better use of FPGA
resources, and allows designers to focus their time evaluating design alternatives. The System Edition includes an
on-chip logic analyzer, high-level synthesis tool, other cutting-edge tools, and the free WebPACK™ version allows
Basys3 designs to be created at no additional cost.
The Basys3.
• 33,280 logic cells in 5200 slices (each slice contains four
6-input LUTs and 8 flip-flops)
• 1,800 Kbits of fast block RAM
• Five clock management tiles, each with a phase-locked
loop (PLL)
• 90 DSP slices
• Internal clock speeds exceeding 450MHz
• On-chip analog-to-digital converter (XADC)
DOC#: 502-183 Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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