Digilent 6003-410-000P-KIT - Manual (Page 55)

XUP Virtex-II Pro Development System www.xilinx.com 55
UG069 (v1.0) March 8, 2005
Using the Expansion Headers and Digilent Expansion Connectors R
7 EXP_IO_47 U5 J3.25 LVTTL
9 EXP_IO_49 W2 J3.29 LVTTL
11 EXP_IO_51 U9 J3.33 LVTTL
13 EXP_IO_53 V4 J3.37 LVTTL
15 EXP_IO_55 Y1 J3.41 LVTTL
17 EXP_IO_57 U8 J3.45 LVTTL
19 EXP_IO_59 V6 J3.49 LVTTL
21 EXP_IO_61 AA2 J4.13 LVTTL
23 EXP_IO_63 V8 J4.17 LVTTL
25 EXP_IO_65 W4 J4.21 LVTTL
27 EXP_IO_67 AB1 J4.25 LVTTL
29 EXP_IO_69 W6 J4.29 LVTTL
31 EXP_IO_71 Y5 J4.33 LVTTL
33 EXP_IO_73 AA4 J4.37 LVTTL
35 EXP_IO_75 W8 J4.41 LVTTL
37 FPGA_TMS H8 – LVTTL
39 LS_EXP_TDO – – LVTTL
2 VCC5V0 – – –
4 EXP_IO_46 U4 J3.23 LVTTL
6 EXP_IO_48 V2 J3.27 LVTTL
8 EXP_IO_50 T9 J3.31 LVTTL
10 EXP_IO_52 V3 J3.35 LVTTL
12 EXP_IO_54 W1 J3.39 LVTTL
14 EXP_IO_56 U7 J3.43 LVTTL
16 EXP_IO_58 V5 J3.47 LVTTL
18 EXP_IO_60 Y2 J4.11 LVTTL
20 EXP_IO_62 V7 J4.15 LVTTL
22 EXP_IO_64 W3 J4.19 LVTTL
24 EXP_IO_66 AA1 J4.23 LVTTL
26 EXP_IO_68 W5 J4.27 LVTTL
28 EXP_IO_70 Y4 J4.31 LVTTL
Table 2-15: Right Digilent Expansion Connector Pinout (Continued)
J5
PIN
Signal
FPGA
Pin
Expansion
Header Pin
IO Type