Digilent 6003-410-000P-KIT - Manual (Page 49)

XUP Virtex-II Pro Development System www.xilinx.com 49
UG069 (v1.0) March 8, 2005
Using the Expansion Headers and Digilent Expansion Connectors R
46 GND – J5.1 J6.1 –
48 GND – J5.1 J6.1 –
50 GND – J5.1 J6.1 –
52 GND – J5.1 J6.1 –
54 GND – J5.1 J6.1 –
56 GND – J5.1 J6.1 –
58 GND – J5.1 J6.1 –
60 GND – J5.1 J6.1 –
Table 2-12: Lower Middle Expansion Header Pinout
J3
Pin
Signal
FPGA
Pin
Digilent
EXP Pin
IO Type
1 VCC2V5 – – –
3 VCC2V5 – – –
5 VCC3V3 – J5.3 J6.3 –
7 VCC3V3 – J5.3 J6.3 –
9 VCC3V3 – J5.3 J6.3 –
11 EXP_IO_40 T3 J5.36 LVTTL
13 EXP_IO_41 T4 J5.37 LVTTL
15 EXP_IO_42 U2 J5.38 LVTTL
17 EXP_IO_43 U3 J5.39 LVTTL
19 EXP_IO_44 T7 J5.40 LVTTL
21 EXP_IO_45 T8 J6.5 LVTTL
23 EXP_IO_46 U4 J6.4 LVTTL
25 EXP_IO_47 U5 J6.7 LVTTL
27 EXP_IO_48 V2 J6.6 LVTTL
29 EXP_IO_49 W2 J6.9 LVTTL
31 EXP_IO_50 T9 J6.8 LVTTL
33 EXP_IO_51 U9 J6.11 LVTTL
35 EXP_IO_52 V3 J6.10 LVTTL
37 EXP_IO_53 V4 J6.13 LVTTL
39 EXP_IO_54 W1 J6.12 LVTTL
Table 2-11: Upper Middle Expansion Header Pinout (Continued)
J2|
Pin
Signal
FPGA
Pin
Digilent
EXP Pin
IO Type