Digilent 6003-410-000P-KIT - Manual (Page 53)

XUP Virtex-II Pro Development System www.xilinx.com 53
UG069 (v1.0) March 8, 2005
Using the Expansion Headers and Digilent Expansion Connectors R
42 GND – J5.1 J6.1 –
44 GND – J5.1 J6.1 –
46 GND – J5.1 J6.1 –
48 GND – J5.1 J6.1 –
50 GND – J5.1 J6.1 –
52 GND – J5.1 J6.1 –
54 GND – J5.1 J6.1 –
56 GND – J5.1 J6.1 –
58 GND – J5.1 J6.1 –
60 GND – J5.1 J6.1 –
Table 2-14: Left Digilent Expansion Connector Pinout
J5
PIN
Signal
FPGA
Pin
Expansion
Header Pin
IO Type
1 GND – J1-4 EVEN PINS –
3 VCC3V3 – – –
5 EXP_IO_9 N5 J1.29 LVTTL
7 EXP_IO_11 L4 J1.33 LVTTL
9 EXP_IO_13 N2 J1.37 LVTTL
11 EXP_IO_15 R9 J1.41 LVTTL
13 EXP_IO_17 M3 J1.45 LVTTL
15 EXP_IO_19 P1 J1.49 LVTTL
17 EXP_IO_21 P7 J2.13 LVTTL
19 EXP_IO_23 N3 J2.17 LVTTL
21 EXP_IO_25 P2 J2.21 LVTTL
23 EXP_IO_27 R7 J2.25 LVTTL
25 EXP_IO_29 P4 J2.29 LVTTL
27 EXP_IO_31 T2 J2.33 LVTTL
29 EXP_IO_33 R5 J2.37 LVTTL
31 EXP_IO_35 R3 J2.41 LVTTL
33 EXP_IO_37 V1 J2.45 LVTTL
35 EXP_IO_39 T6 J2.49 LVTTL
Table 2-13: Bottom Expansion Header Pinout (Continued)
J4
Pin
Signal
FPGA
Pin
Digilent
EXP Pin
IO Type