Teledyne LeCroy PeRT3 Phoenix System - Manual (Page 65)

Teledyne LeCroy PeRT
3
Phoenix System User Manual 63
System Control Ribbon ‐‐ Pattern Tab Teledyne LeCroy
System Control Ribbon -- Pattern Tab
For discussion of the controls available under the Pattern tab, see “Creating Test Patterns”
on page 83 .
System Control Ribbon -- Options Tab
Clicking on the Options tab brings up the following panels:
Default Settings
The Default Settings panel (see Figure 6.23 on page 63 ) allows the user to establish the
default values that appear whenever a protocol, number of channels, or Host/Device
setting is required. Establishing these default values saves the user time in not needing to
change values constantly when working on a particular development project.
The Auto display graph option, if selected, will result in a new graph being displayed and
updated in real time whenever you run a test that records results.
The Show connect log option, if selected, will result in a connection log being displayed.
Figure 6.23: Default settings Panel
Pattern Checking
The PeRT
3
system normally validates patterns to ensure they conform with the
specification requirements for the type of testing taking place.
As an example, if testing Frame Error Rate of a SATA device, the pattern must be a valid
SATA Frame without any encoding errors and with a correct CRC. If the selected pattern is
not a valid SATA frame, pattern checking will detect this and issue a warning and
substitute a default pattern that is valid for the specified test mode.
The Pattern Checking panel (see Figure 6.24 on page 64 )allows the user to control what
types of pattern checking take place, and in rare instances, to turn off the automatic
pattern checking for specific tests. Consider a case in which the user wanted to
deliberately send an invalid frame to test the DUT's higher level protocol handling logic.
Deliberately sending an invalid frame should result in a 100% frame error rate as the DUT
should reject every instance of the frame that is sent. Similarly during SATA bit error ratio
testing, the pattern must contain ALIGNs at the proper intervals for the device to work. By