Rainbow Electronics Atmega169L - Manual (Page 91)

91
ATmega169V/L
2514A–AVR–08/02
Output Compare Register A –
OCR0A
The Output Compare Register A contains an 8-bit value that is continuously compared
with the counter value (TCNT0). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC0A pin.
Timer/Counter 0 Interrupt
Mask Register – TIMSK0
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one),
the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt
is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is
set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if
a n o verflo w in Ti mer/Coun ter0 occurs, i .e ., when the TO V0 b it i s set in th e
Timer/Counter 0 Interrupt Flag Register – TIFR0.
Timer/Counter 0 Interrupt Flag
Register – TIFR0
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0
and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF0A is
cl eared b y w riting a l ogi c o ne to the flag . Wh en the I-bit in SREG , O CIE0A
(Timer/Counter0 Compare match Interrupt Enable), and OCF0A are set (one), the
Timer/Counter0 Compare match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0
( T im er /Co u nte r0 O v er flo w In ter ru p t En ab l e ), a n d TO V 0 ar e se t (o n e) , th e
Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is
set when Timer/Counter0 changes counting direction at 0x00.
Bit 7 6 5 4 3 2 1 0
OCR0A[7:0] OCR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – – – – – OCIE0A TOIE0 TIMSK0
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – – – – – OCF0A TOV0 TIFR0
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0