Data modes, Atmega169v/l – Rainbow Electronics Atmega169L User Manual

Page 149

149

ATmega169V/L

2514A–AVR–08/02

Data Modes

There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits CPHA and CPOL. The SPI data transfer formats
are shown in Figure 66 and Figure 67. Data bits are shifted out and latched in on oppo-
site edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is
clearly seen by summarizing Table 67 and Table 68, as done below:

Figure 66. SPI Transfer Format with CPHA = 0

Figure 67. SPI Transfer Format with CPHA = 1

Table 70. CPOL Functionality

Leading Edge

Trailing eDge

SPI Mode

CPOL=0, CPHA=0

Sample (Rising)

Setup (Falling)

CPOL=0, CPHA=1

Setup (Rising)

Sample (Falling)

CPOL=1, CPHA=0

Sample (Falling)

Setup (Rising)

CPOL=1, CPHA=1

Setup (Falling)

Sample (Rising)

Bit 1
Bit 6

LSB
MSB

SCK (CPOL = 0)
mode 0

SAMPLE I
MOSI/MISO

CHANGE 0
MOSI PIN

CHANGE 0
MISO PIN

SCK (CPOL = 1)
mode 2

MSB
LSB

Bit 6
Bit 1

Bit 5
Bit 2

Bit 4
Bit 3

Bit 3
Bit 4

Bit 2
Bit 5

MSB first (DORD = 0)
LSB first (DORD = 1)

SCK (CPOL = 0)
mode 1