Rainbow Electronics Atmega169L - Manual (Page 183)

183
ATmega169V/L
2514A–AVR–08/02
Start Condition Detector The start condition detector is shown in Figure 80. The SDA line is delayed (in the range
of 50 to 300 ns) to ensure valid sampling of the SCL line.
The start condition detector is working asynchronously and can therefore wake up the
processor from the Power-down sleep mode. However, the protocol used might have
restrictions on the SCL hold time. Therefore, when using this feature in this case the
Oscillator start-up time set by the CKSEL Fuses (see “Clock Systems and their Distribu-
tion” on page 23) must also be taken into the consideration.
Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative
tasks due to its flexible design.
Half-duplex Asynchronous
Data Transfer By utilizing the Shift Register in Three-wire mode, it is possible to implement a more
compact and higher performance UART than by software only.
4-bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note
that if the counter is clocked externally, both clock edges will generate an increment.
12-bit Timer/Counter Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
Edge Triggered External
Interrupt By setting the counter to maximum value (F) it can function as an additional external
interrupt. The overflow flag and interrupt enable bit are then used for the external inter-
rupt. This feature is selected by the USICS1 bit.
Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock
strobe.
USI Register
Descriptions
USI Data Register – USIDR
The USI uses no buffering of the serial register, i.e., when accessing the Data Register
(USIDR) the serial register is accessed directly. If a serial clock occurs at the same cycle
the register is written, the register will contain the value written and no shift is performed.
A (left) shift operation is performed depending of the USICS1..0 bits setting. The shift
operation can be controlled by an external clock edge, by a Timer/Counter0 overflow, or
directly by software using the USICLK strobe bit. Note that even when no wire mode is
selected (USIWM1..0 = 0) both the external data input (DI/SDA) and the external clock
input (USCK/SCL) can still be used by the Shift Register.
The output pin in use, DO or SDA depending on the wire mode, is connected via the out-
put latch to the most significant bit (bit 7) of the Data Register. The output latch is open
(transparent) during the first half of a serial clock cycle when an external clock source is
selected (USICS1 = 1), and constantly open when an internal clock source is used
(USICS1 = 0). The output will be changed immediately when a new MSB written as long
as the latch is open. The latch ensures that data input is sampled and data output is
changed on opposite clock edges.
Bit 7 6 5 4 3 2 1 0
MSB LSB USIDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0