Standby mode, Minimizing power consumption, Analog to digital converter – Rainbow Electronics Atmega169L User Manual
Page 34: Analog comparator, Atmega169v/l
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ATmega169V/L
2514A–AVR–08/02
The LCD controller and Timer/Counter2 can be clocked both synchronously and asyn-
chronously in Power-save mode. The clock source for the two modules can be selected
independent of each other. If neither the LCD controller nor the Timer/Counter2 is using
the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If neither
the LCD controller nor the Timer/Counter2 is using the synchronous clock, the clock
source is stopped during sleep. Note that even if the synchronous clock is running in
Power-save, this clock is only available for the LCD controller and Timer/Counter2.
Standby Mode
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,
the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to
Power-down with the exception that the Oscillator is kept running. From Standby mode,
the device wakes up in six clock cycles.
Notes:
1. Only recommended with external crystal or resonator selected as clock source.
2. If either LCD controller or Timer/Counter2 is running in asynchronous mode.
3. For INT0, only level interrupt.
Minimizing Power
Consumption
There are several issues to consider when trying to minimize the power consumption in
an AVR controlled system. In general, sleep modes should be used as much as possi-
ble, and the sleep mode should be selected so that as few as possible of the device’s
functions are operating. All functions not needed should be disabled. In particular, the
following modules may need special consideration when trying to achieve the lowest
possible power consumption.
Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should
be disabled before entering any sleep mode. When the ADC is turned off and on again,
the next conversion will be an extended conversion. Refer to “Analog to Digital Con-
verter” on page 191 for details on ADC operation.
Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When
entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In
other sleep modes, the Analog Comparator is automatically disabled. However, if the
Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog
Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref-
erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on
page 188 for details on how to configure the Analog Comparator.
Table 15. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Oscillators
Wake-up Sources
Sleep Mode
clk
CPU
clk
FLASH
clk
IO
clk
ADC
clk
ASY
Main Clock
Source
Enabled
Timer
Osc
Enabled
INT0
and Pin
Change
USI Start
Condition
LCD
Controller Timer2
SPM/
EEPROM
Ready
ADC
Other
I/O
Idle
X
X
X
X
X
X
X
X
X
X
X
X
ADC Noise
Reduction
X
X
X
X
X
(3)
X
X
X
X
X
Power-down
X
(3)
X
Power-save
X
X
X
(3)
X
X
X
Standby
(1)
X
X
(3)
X