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Timer/counter prescaler, General timer/counter control register – gtccr, Atmega169v/l – Rainbow Electronics Atmega169L User Manual

Page 141: 8, clk, 32, clk, 64, clk, 128, clk, 256, and clk, 1024. additionally, clk

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141

ATmega169V/L

2514A–AVR–08/02

Timer/Counter Prescaler

Figure 63. Prescaler for Timer/Counter2

The clock source for Timer/Counter2 is named clk

T2S

. clk

T2S

is by default connected to

the main system I/O clock clk

I

O

. By setting the AS2 bit in ASSR, Timer/Counter2 is asyn-

chronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real
Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from
Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve
as an independent clock source for Timer/Counter2. The Oscillator is optimized for use
with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is not
recommended.

For Timer/Counter2, the possible prescaled selections are: clk

T2S

/8, clk

T2S

/32, clk

T2S

/64,

clk

T2S

/128, clk

T2S

/256, and clk

T2S

/1024. Additionally, clk

T2S

as well as 0 (stop) may be

selected. Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to
operate with a predictable prescaler.

General Timer/Counter
Control Register – GTCCR

• Bit 1 – PSR2: Prescaler Reset Timer/Counter2

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally
cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating
in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit
will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7
– TSM: Timer/Counter Synchronization Mode” on page 93
for a description of the
Timer/Counter Synchronization mode.

10-BIT T/C PRESCALER

TIMER/COUNTER2 CLOCK SOURCE

clk

I/O

clk

T2S

TOSC1

AS2

CS20

CS21

CS22

clk

T2S

/8

clk

T2S

/64

clk

T2S

/128

clk

T2S

/1024

clk

T2S

/256

clk

T2S

/32

0

PSR2

Clear

clk

T2

Bit

7

6

5

4

3

2

1

0

TSM

PSR2

PSR10

GTCCR

Read/Write

R/W

R

R

R

R

R

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0