Texas Instruments TMS320C645X - Manual (Page 92)

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SRIO Registers
Table 28. Serial Rapid IO (SRIO) Registers (continued)
Offset Acronym Register Description Section
0x0584 QUEUE1_TXDMA_C Queue Transmit DMA Completion Pointer Register 1 Section 5.50
P
0x0588 QUEUE2_TXDMA_C Queue Transmit DMA Completion Pointer Register 2 Section 5.50
P
0x058C QUEUE3_TXDMA_C Queue Transmit DMA Completion Pointer Register 3 Section 5.50
P
0x0590 QUEUE4_TXDMA_C Queue Transmit DMA Completion Pointer Register 4 Section 5.50
P
0x0594 QUEUE5_TXDMA_C Queue Transmit DMA Completion Pointer Register 5 Section 5.50
P
0x0598 QUEUE6_TXDMA_C Queue Transmit DMA Completion Pointer Register 6 Section 5.50
P
0x059C QUEUE7_TXDMA_C Queue Transmit DMA Completion Pointer Register 7 Section 5.50
P
0x05A0 QUEUE8_TXDMA_C Queue Transmit DMA Completion Pointer Register 8 Section 5.50
P
0x05A4 QUEUE9_TXDMA_C Queue Transmit DMA Completion Pointer Register 9 Section 5.50
P
0x05A8 QUEUE10_TXDMA_ Queue Transmit DMA Completion Pointer Register 10 Section 5.50
CP
0x05AC QUEUE11_TXDMA_ Queue Transmit DMA Completion Pointer Register 11 Section 5.50
CP
0x05B0 QUEUE12_TXDMA_ Queue Transmit DMA Completion Pointer Register 12 Section 5.50
CP
0x05B4 QUEUE13_TXDMA_ Queue Transmit DMA Completion Pointer Register 13 Section 5.50
CP
0x05B8 QUEUE14_TXDMA_ Queue Transmit DMA Completion Pointer Register 14 Section 5.50
CP
0x05BC QUEUE15_TXDMA_ Queue Transmit DMA Completion Pointer Register 15 Section 5.50
CP
0x0600 QUEUE0_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 0 Section 5.51
DP
0x0604 QUEUE1_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 1 Section 5.51
DP
0x0608 QUEUE2_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 2 Section 5.51
DP
0x060C QUEUE3_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 3 Section 5.51
DP
0x0610 QUEUE4_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 4 Section 5.51
DP
0x0614 QUEUE5_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 5 Section 5.51
DP
0x0618 QUEUE6_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 6 Section 5.51
DP
0x061C QUEUE7_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 7 Section 5.51
DP
0x0620 QUEUE8_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 8 Section 5.51
DP
0x0624 QUEUE9_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 9 Section 5.51
DP
0x0628 QUEUE10_RXDMA_ Queue Receive DMA Head Descriptor Pointer Register 10 Section 5.51
HDP
0x062C QUEUE11_RXDMA_ Queue Receive DMA Head Descriptor Pointer Register 11 Section 5.51
HDP
92 Serial RapidIO (SRIO) SPRU976 – March 2006
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