Texas Instruments TMS320C645X - Manual (Page 7)

52 Load/Store Module Interrupt Condition Routing Registers
............................................................
82
53 Error, Reset, and Special Event Interrupt Condition Routing Registers ............................................ 83
54 Sharing of ISDR Bits ....................................................................................................... 84
55 Example Diagram of Interrupt Status Decode Register Mapping
....................................................
84
56 INTDSTn_Decode Interrupt Status Decode Register ................................................................. 85
57 INTDSTn_RATE_CNTL Interrupt Rate Control Register .............................................................. 86
58 Peripheral ID Register (PID)
..............................................................................................
99
59 Peripheral Control Register (PCR) ..................................................................................... 100
60 Peripheral Settings Control Register (PER_SET_CNTL) ............................................................ 101
61 Peripheral Global Enable Register (GBL_EN)
........................................................................
104
62 Peripheral Global Enable Status Register (GBL_EN_STAT) ....................................................... 105
63 Block n Enable Register (BLKn_EN) ................................................................................... 106
64 Block n Enable Status Register (BLKn_EN_STAT)
..................................................................
107
65 RapidIO DEVICEID1 Register (DEVICEID_REG1) .................................................................. 108
66 RapidIO DEVICEID2 Register (DEVICEID_REG2) .................................................................. 109
67 Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTLn)
..............................................
110
68 Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTLn) ................................................. 111
69 SERDES Receive Channel Configuration Registers n (SERDES_CFGRXn_CNTL) ............................ 112
70 SERDES Transmit Channel Configuration Registers n (SERDES_CFGTXn_CNTL)
...........................
114
71 SERDES Macros CFG (0-3) Registers (SERDES_CFGn_CNTL) ................................................. 116
72 DOORBELLn Interrupt Status Register (DOORBELLn_ICSR) ..................................................... 117
73 DOORBELLn Interrupt Clear Register (DOORBELLn_ICCR)
......................................................
118
74 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) ............................................................... 119
75 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) ................................................................ 120
76 TX CPPI Interrupt Status Register (TX_CPPI_ICSR)
................................................................
121
77 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) ................................................................. 122
78 LSU Status Interrupt Register (LSU_ICSR) ........................................................................... 123
79 LSU Clear Interrupt Register (LSU _ICCR)
...........................................................................
124
80 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) .......................... 125
81 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) ........................... 126
82 DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR)
.......................................
127
83 DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2) ................................... 128
84 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) ................................................ 129
85 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2)
...............................................
130
86 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) ................................................. 131
87 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) ............................................... 132
88 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0)
................................................
133
89 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) ................................................ 134
90 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) ................................................ 135
91 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3)
................................................
136
92 Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR) ............ 137
93 Error, Reset, and Special Event Interrupt Condition Routing Register 2 (ERR_RST_EVNT_ICRR2) ........ 138
94 Error, Reset, and Special Event Interrupt Condition Routing Register 3 (ERR_RST_EVNT_ICRR3)
........
139
95 INTDSTn Interrupt Status Decode Registers (INTDSTn_DECODE) ............................................... 140
96 INTDSTn Interrupt Rate Control Registers (INTDSTn_RATE_CNTL) ............................................. 141
97 LSUn Control Register 0 (LSUn_REG0)
...............................................................................
142
98 LSUn Control Register 1 (LSUn_REG1) ............................................................................... 143
99 LSUn Control Register 2 (LSUn_REG2) ............................................................................... 144
100 LSUn Control Register 3 (LSUn_REG3)
...............................................................................
145
101 LSUn Control Register 4 (LSUn_REG4) ............................................................................... 146
102 LSUn Control Register 5 (LSUn_REG5) ............................................................................... 147
103 LSUn Control Register 6 (LSUn_REG6)
...............................................................................
148
104 LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n) ................................................... 149
SPRU976 – March 2006 List of Figures 7
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