Texas Instruments TMS320C645X - Manual (Page 6)

List of Figures
1 RapidIO Architectural Hierarchy .......................................................................................... 15
2 RapidIO Interconnect Architecture ....................................................................................... 16
3 Serial RapidIO Device to Device Interface Diagrams
.................................................................
17
4 SRIO Peripheral Block Diagram .......................................................................................... 20
5 Operation Sequence ....................................................................................................... 21
6 1x/4x RapidIO Packet Data Stream (Streaming-Write Class)
........................................................
22
7 Serial RapidIO Control Symbol Format .................................................................................. 22
8 SRIO Conceptual Block Diagram ........................................................................................ 25
9 Load/Store Data Transfer Diagram
......................................................................................
32
10 Load/Store Registers for RapidIO (Address Offset: LSU1 0x400-0x418, LSU2 0x420-0x438, LSU3
0x440-0x458, LSU4 0x460-0x478)
.......................................................................................
33
11 LSU Registers Timing ..................................................................................................... 35
12 Example Burst NWRITE_R ............................................................................................... 36
13 Load/Store Module Data Flow
............................................................................................
37
14 CPPI RX Scheme for RapidIO ............................................................................................ 41
15 Message Request Packet ................................................................................................. 41
16 Queue Mapping Table (Address Offset: 0x0800 - 0x08FC)
..........................................................
42
17 Queue Mapping Register RXU_MAP_Ln ............................................................................... 43
18 Queue Mapping Register RXU_MAP_Hn ............................................................................... 43
19 RX Buffer Descriptor Fields
...............................................................................................
44
20 RX CPPI Mode Explanation .............................................................................................. 47
21 CPPI Boundary Diagram .................................................................................................. 48
22 TX Buffer Descriptor Fields
...............................................................................................
49
23 Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) .............................. 52
24 RX Buffer Descriptor ....................................................................................................... 57
25 TX Buffer Descriptor
.......................................................................................................
58
26 Doorbell Operation ......................................................................................................... 59
27 Flow Control Table Entry Registers (Address Offset 0x0900 - 0x093C) ............................................ 61
28 Transmit Source Flow Control Masks
...................................................................................
62
29 Configuration Bus Example
...............................................................................................
63
30 DMA Example .............................................................................................................. 64
31 GBL_EN (Address 0x0030)
...............................................................................................
65
32 GBL_EN_STAT (Address 0x0034)
.......................................................................................
65
33 BLK0_EN (Address 0x0038) .............................................................................................. 65
34 BLK0_EN_STAT (Address 0x003C) ..................................................................................... 66
35 BLK1_EN (Address 0x0040)
..............................................................................................
66
36 BLK1_EN_STAT (Address 0x0044) ..................................................................................... 66
37 BLK8_EN (Address 0x0078) .............................................................................................. 66
38 BLK8_EN_STAT (Address 0x007C)
.....................................................................................
66
39 Emulation Control (Peripheral Control Register PCR 0x0004) ....................................................... 68
40 Bootload Operation ........................................................................................................ 72
41 Detectable Errors
...........................................................................................................
73
42 RapidIO DOORBELL Packet for Interrupt Use ......................................................................... 74
43 DOORBELL0 Interrupt Registers for Direct I/O Transfers ............................................................ 76
44 DOORBELL1 Interrupt Registers for Direct I/O Transfers
............................................................
76
45 DOORBELL2 Interrupt Registers for Direct I/O Transfers ............................................................ 77
46 DOORBELL3 Interrupt Registers for Direct I/O Transfers ............................................................ 77
47 RX_CPPI Interrupts Using Messaging Mode Data Transfers
........................................................
78
48 TX _CPPI Interrupts Using Messaging Mode Data Transfers ........................................................ 78
49 LSU Load/Store Module Interrupts ....................................................................................... 79
50 ERR_RST_EVNT Error, Reset, and Special Event Interrupt
.........................................................
80
51 Doorbell 0 Interrupt Condition Routing Registers ...................................................................... 81
6 List of Figures SPRU976 – March 2006
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