Texas Instruments TMS320C645X - Manual (Page 137)

www.ti.com
5.36 Error, Reset, and Special Event Interrupt Condition Routing Register
SRIO Registers
(ERR_RST_EVNT_ICRR)
Figure 92. Error, Reset, and Special Event Interrupt Condition Routing Register
(ERR_RST_EVNT_ICRR)
31-16
Reserved
R-0x00
LEGEND: R = Read only; -n = value after reset
15-12 11-8 7-4 3-0
Reserved ICR2 ICR1 ICR0
R-0x00 RW-0x00 RW-0x00 RW-0x00
LEGEND: R = Read only; -n = value after reset
Table 66. Error, Reset, and Special Event Interrupt Condition Routing Register
(ERR_RST_EVNT_ICRR) Field Descriptions
Bit Field Value Description
31-12 Reserved Reserved
11-8 ICR2 Logical Layer Error Management Event Capture routing
7-4 ICR1 Routing of Port-write-in request received on any port
3-0 ICR0 Routing of Multi-cast event control symbol interrupt received on any port
SPRU976 – March 2006 Serial RapidIO (SRIO) 137
Submit Documentation Feedback