Texas Instruments TMS320C645X - Manual (Page 82)

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Interrupt Conditions
Figure 52. Load/Store Module Interrupt Condition Routing Registers
LSU_ICRR0 (Address Offset 0x02E0)
31 28 27 24 23 20 19 16
ICR7 ICR6 ICR5 ICR4
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR3 ICR2 ICR1 ICR0
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LEGEND: R = Read, W = Write, n = value at reset
LSU_ICRR1 (Address Offset 0x02E4)
31 28 27 24 23 20 19 16
ICR15 ICR14 ICR13 ICR12
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR11 ICR10 ICR9 ICR8
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LEGEND: R = Read, W = Write, n = value at reset
LSU_ICRR2 (Address Offset 0x02E8)
31 28 27 24 23 20 19 16
ICR23 ICR22 ICR21 ICR20
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR19 ICR18 ICR17 ICR16
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LEGEND: R = Read, W = Write, n = value at reset
LSU_ICRR3 (Address Offset 0x02EC)
31 28 27 24 23 20 19 16
ICR31 ICR30 ICR29 ICR28
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR27 ICR26 ICR25 ICR24
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LEGEND: R = Read, W = Write, n = value at reset
Serial RapidIO (SRIO) 82 SPRU976 – March 2006
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