Texas Instruments TMS320C645X User Manual
Page 209
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SRIO Registers
Table 134. Port IP Mode CSR (SP_IP_MODE) Field Descriptions (continued)
Bit
Field
Value
Description
3
RST_EN
Reset Interrupt Enable. If enabled, the interrupt signal is High when the 4 reset control symbols are
received in a sequence
0b
Reset interrupt disable
1b
Reset interrupt enable
2
RST_CS
Reset received status bit. It is set when 4 reset control symbols are received in a sequence. Once
set, it remains set until written with logic 1 to clear. The rst_irq output signal is driven by this bit.
1
PW_EN
Port-Write-In Interrupt Enable. If enabled, the interrupt signal is High when the Port-Write-In request
is received
0b
Port-Write-In interrupt disable
1b
Port-Write-In interrupt enable
0
PW_IRQ
Port-Write-In Request interrupt is set when the Port-Write-In request is received. The payload is
captured. Once set, it remains set until written with logic 1 to clear. The pw_irq output signal is
driven by this bit.
SPRU976 – March 2006
Serial RapidIO (SRIO)
209