Texas Instruments TMS320C645X - Manual (Page 18)

www.ti.com
1.3 Standards
1.4 External Devices Requirements
Overview
Features Not Supported:
•
Compliance with the Global Shared Memory specification (GSM)
•
8/16 LP-LVDS compatible
•
Destination support of RapidIO Atomic Operations
•
Simultaneous mixing of frequencies between 1X ports (all ports must be the same frequency)
•
Target atomic operations (including increment, decrement, test-and-swap, set, and clear) for internal
L2 memory and registers
The SRIO peripheral is compliant to V1.2 of the RapidIO Interconnect Specification and V1.2 of the
LP-Serial specification.
Table 1. RapidIO Documents and Links
Document Link Description
Official RapidIO Web Site http://www.RapidIO.org Various associated docs
SRIO provides a seamless interface to all devices which are compliant to V1.2 of the LP-Serial RapidIO
specification. This includes ASIC, microprocessor, DSP, and switch fabric devices from multiple vendors.
Compliance to the specification can be verified with bus-functional models available through the RapidIO
Trade Association, as well as test suites currently available for licensing.
Serial RapidIO (SRIO) 18 SPRU976 – March 2006
Submit Documentation Feedback