104 port ip mode csr (sp_ip_mode), Sp_ip_mode), Descriptions – Texas Instruments TMS320C645X User Manual
Page 208: Section 5.104
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5.104
Port IP Mode CSR (SP_IP_MODE)
SRIO Registers
Figure 160. Port IP Mode CSR (SP_IP_MODE)
31-30
29
28
27
26
25
24-16
SP_MODE
IDLE_
TX_FI
PW_DI
TGT_I
SELF_
Reserved
ERR_
FO_B
S
D_DIS
RST
DIS
YPAS
S
R-0x00
RW-
RW-
RW-
R-
RW-
R-0x00
0x00
0x00
0x00
0x00
0x00
LEGEND: R = Read only; -n = value after reset
15-6
5
4
3
2
1
0
Reserved
MLTC
MLTC
RST_
RST_
PW_E
PW_IR
_EN
_IRQ
EN
CS
N
Q
R-0x00
RW-
RC-
RW-
RC-
RW-
RC-
0x00
0x00
0x00
0x00
0x00
0x00
LEGEND: R = Read only; -n = value after reset
Table 134. Port IP Mode CSR (SP_IP_MODE) Field Descriptions
Bit
Field
Value
Description
31-30
SP_MODE
SRIO Port IP Mode of operation.
00
1x/4x LP-Serial RapidIO Specification
01
4 ports (1x mode each)
10
Reserved
11
Reserved
29
IDLE_ERR_DIS
IDLE Error checking disable.
0
Error checking enabled (default), only |K|, |A| and |R| characters are available. If input receives any
other characters in idle sequence, it should enter the Input-Error-stopped state.
1
Error checking disabled, all not idle or invalid characters during idle sequence are ignored
28
TX_FIFO_BYPAS
Transmit FIFO
S
0
The TX_FIFO is operational (Default)
1
The TX_FIFO is bypassed. The txbclk and the sys_clk must be locked during operation, but the
phase variation up to 1 clock cycle is allowable. The 4 deep FIFO is used to accommodate the
phase difference.
27
PW_DIS
Port-Write Disable.
0
Enable Port-Write Error reporting (default)
1
Disable Port-Write Error reporting
26
TGT_ID_DIS
Destination ID Decode Disable- Definition of packet acceptance by the physical layer.
0
Packet accepted if DestID = Base ID. When DestID is not equal to Base ID, the packet is ignored;
i.e., it is accepted by RapidIO port but is not forwarded to logical layer.
1
Packet accepted with any DestID and forwarded to the logical layer.
25
SELF_RST
Self reset enable, when 4 Link-Request Reset Control Symbols are accepted.
0
Self reset interrupt disabled (default), interrupt signal is asserted
1
Self reset interrupt enabled, the reset signal is asserted by the SRIO_TE reset controller. The
SRIO_TE configuration registers are set to the default value after reset and loose a boot
initialization values.
24-6
Reserved
Reserved
5
MLTC_EN
Multicast-Event Interrupt Enable. If enabled, the interrupt signal is High when the Multicast-Event
control symbol is received by any port.
0b
Multicast interrupt disable
1b
Multicast interrupt enable
4
MLTC_IRQ
Multicast-Event Interrupt Status bit. It is High when the Multicast-Event control symbol is received
by any port. Once set, it remains set until written with logic 1 to clear. The mltc_irq output signal is
driven by this bit.
208
Serial RapidIO (SRIO)
SPRU976 – March 2006