Texas Instruments TMS320C645X - Manual (Page 173)

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5.71 Processing Element Logical Layer Control CSR (PE_LL_CTL)
SRIO Registers
Figure 127. Processing Element Logical Layer Control CSR (PE_LL_CTL)
31-16
Reserved
R-0x0000
LEGEND: R = Read only; -n = value after reset
15-3 2-0
Reserved EXTENDED_ADDRESS
ING_CONTROL
R-0x0000 RW-0x0001
LEGEND: R = Read only; -n = value after reset
Table 101. Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions
Bit Field Value Description
31-3 Reserved Reserved
2-0 EXTENDED_ADD Controls the number of address bits generated by the PE as a source and processed by the PE as
RESSING_CONT the target of an operation. All other encodings reserved.
ROL
100b PE supports 66 bit addresses
010b PE supports 50 bit addresses
001b PE supports 34 bit addresses
SPRU976 – March 2006 Serial RapidIO (SRIO) 173
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