Texas Instruments TMS320C645X - Manual (Page 70)

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SRIO Functional Description
2.3.11.2 PLL, Ports, Device ID and Data Rate Initializations
For example, Enable pll, 333MHz, 4p1x, x20. 3.125 Gbps, full rate, ½ rate, ¼ rate:
if (srio4p1x_mode){
rdata = SRIO_REGS->PER_SET_CNTL;
wdata = 0x0000014F; 4p1x
mask = 0x000001FF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata ; // enable pll
}
else{
wdata = 0x0000004F; // enable pll, 1p4x
rdata = SRIO_REGS->PER_SET_CNTL;
mask = 0x000001FF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata ; // enable pll, 1p1x/4x
}
rdata = SRIO_REGS->SERDES_CFG0_CNTL;
wdata = 0x0000000D;
mask = 0x00000FFF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->SERDES_CFG0_CNTL = mdata ; // JADIS 3.125 Gbps
SRIO_REGS->SERDES_CFG1_CNTL = mdata ; // JADIS 3.125 Gbps
SRIO_REGS->SERDES_CFG2_CNTL = mdata ; // JADIS 3.125 Gbps
SRIO_REGS->SERDES_CFG4_CNTL = mdata ; // JADIS 3.125 Gbps
SRIO_REGS->SERDES_CFGRX0_CNTL = 0x00081101 ; // enable rx, rate 1
SRIO_REGS->SERDES_CFGRX1_CNTL = 0x00081101 ; // enable rx, rate 1
SRIO_REGS->SERDES_CFGRX2_CNTL = 0x00081101 ; // enable rx, rate 1
SRIO_REGS->SERDES_CFGRX3_CNTL = 0x00081101 ; // enable rx, rate 1
SRIO_REGS->SERDES_CFGTX0_CNTL = 0x00010801 ; // enable tx, rate 1
SRIO_REGS->SERDES_CFGTX1_CNTL = 0x00010801 ; // enable tx, rate 1
SRIO_REGS->SERDES_CFGTX2_CNTL = 0x00010801 ; // enable tx, rate 1
SRIO_REGS->SERDES_CFGTX3_CNTL = 0x00010801 ; // enable tx, rate 1
2.3.11.3 Peripheral Initializations
Set Device ID Registers
rdata = SRIO_REGS->DEVICEID_REG1;
wdata = 0x00ABBEEF;
mask = 0x00FFFFFF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->DEVICEID_REG1 = mdata ; // id-16b=BEEF, id-08b=AB
rdata = SRIO_REGS->DEVICEID_REG2;
wdata = 0x00ABBEEF;
mask = 0x00FFFFFF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->DEVICEID_REG2 = mdata ; // id-16b=BEEF, id-08b=AB
SRIO_REGS->PER_SET_CNTL = 0x00000000; // bootcmpl=0
SRIO_REGS->DEV_ID = 0xBEEF0030 ; // id=BEEF, ti=0x0030
SRIO_REGS->DEV_INFO = 0x00000000 ; // 0
SRIO_REGS->ASBLY_ID = 0x00000030 ; // ti=0x0030
SRIO_REGS->ASBLY_INFO = 0x00000000; // 0x0000, next ext=0x0100
SRIO_REGS->PE_FEAT = 0x20000019 ; // proc, bu ext, 16-bit ID, 34-bit addr
SRIO_REGS->SW_PORT = 0x00000400; // 4 ports
SRIO_REGS->SRC_OP = 0x0000FDF4; // all
SRIO_REGS->DEST_OP = 0x0000FC04; // all except atomic
SRIO_REGS->PE_LL_CTL = 0x00000001; // 34-bit addr
SRIO_REGS->LCL_CFG_HBAR = 0x00000000 ; // 0
SRIO_REGS->LCL_CFG_BAR = 0x00000000; // 0
SRIO_REGS->BASE_ID = 0x00ABBEEF; // 16b-id=BEEF, 08b-id=AB
SRIO_REGS->HOST_BASE_ID_LOCK = 0x0000BEEF; // id=BEEF, lock
SRIO_REGS->COMP_TAG = 0x00000000; // not touched
SRIO_REGS->SP_IP_DISCOVERY_TIMER = 0x90000000;// 0, short cycles for sim
//INIT_MAC0
if (srio4p1x_mode){
SRIO_REGS->SP_IP_MODE = 0x44000000; // Jadis mltc/rst/pw enable, clear
70 Serial RapidIO (SRIO) SPRU976 – March 2006
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