Texas Instruments TMS320C645X User Manual

Page 47

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Switch

Endpoint

Open

Full

Open

Full

Retry

Action

Retry

Scenario A - Default

Scenario B - In order mode

Data flow destined for the

same Rx Queue

Rx Queue Status when

packet arrives

Rx Queue Status when

packet arrives

Records SourceID/letter of

first retry packet

SRIO Functional Description

Figure 20. RX CPPI Mode Explanation

In addition, multiple messages can be interleaved at the receive port due to ordering within a connected
switch’s output queue. This can occur when using a single or multiple priorities. The RX CPPI block must
handle simultaneous interleaved multi-segment messages. This implies that state information (write
pointers and srcID) must be maintained on each simultaneous message to properly store the segments in
memory. The number of simultaneous transactions supported directly impacts the number of states to be
stored, and the size of the buffer descriptor memory outside the peripheral. With this in mind, the
peripheral’s supported buffer descriptor SRAM is parameterizable. A minimum size of 1.25KB is
recommended, which will allow up to 64 buffer descriptors to be stored at any given time for one core.
These buffer descriptors can be configured to support any combination of single and multi-segment
messages. For example, if the application only handles single-segment messages, all 64 buffers can be
allotted to that queue. Note that a given RX queue can contain packets of all priorities which have been
directed from any of the receive ports.

A CPU may wish to stop receiving messages and reclaim buffers belonging to a specific queue. This is
called queue teardown. The CPU initiates a RX queue teardown by writing to the RX Queue Teardown
command register.

SPRU976 – March 2006

Serial RapidIO (SRIO)

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