Texas Instruments TMS320C645X User Manual
Page 35
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LSU_Reg1
T0
T1
T2
T3
T4
T5
Tn
Valid
LSU_Reg2
Valid
LSU_Reg3
Valid
LSU_Reg4
Valid
LSU_Reg5
Valid
Rdy/BSY
Completion
Valid
Valid
After Transaction Completes
SRIO Functional Description
Figure 11. LSU Registers Timing
The following code illustrates an LSU registers programming example.
SRIO_REGS->;LSU1_Reg0 =
CSL_FMK( SRIO_LSU1_REG0_RAPIDIO_ADDRESS_MSB,0 );
//poll mode, extended address type 2,5,6
SRIO_REGS->;LSU1_Reg1 =
CSL_FMK( SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET,(int);rcvBuff1[0] );
//32bit = type 2,5,6. 24bit = type 8
SRIO_REGS->;LSU1_Reg2 =
CSL_FMK( SRIO_LSU1_REG2_DSP_ADDRESS, (int);xmtBuff1[0]);
SRIO_REGS->;LSU1_Reg3 =
CSL_FMK( SRIO_LSU1_REG3_BYTE_COUNT,byte_count );
SRIO_REGS->;LSU1_Reg4 =
CSL_FMK( SRIO_LSU1_REG4_OUTPORTID,0 )|
CSL_FMK( SRIO_LSU1_REG4_PRIORITY,0 )|
CSL_FMK( SRIO_LSU1_REG4_XAMBS,0 )|
//no extended address
CSL_FMK( SRIO_LSU1_REG4_ID_SIZE,1 )|
//tt = 0b01
CSL_FMK( SRIO_LSU1_REG4_DESTID,0xBEEF )|
CSL_FMK( SRIO_LSU1_REG4_INTERRUPT_REQ,1 );
//0 = event-driven, 1 = poll
SRIO_REGS->;LSU1_Reg5 =
CSL_FMK( SRIO_LSU1_REG5_DRBLL_INFO,0x0000 )|
CSL_FMK( SRIO_LSU1_REG5_HOP_COUNT,0x00 )|
CSL_FMK( SRIO_LSU1_REG5_PACKET_TYPE,type );
//REQ_NWRITE
illustrates an example of the data flow and field mappings for a burst NWRITE_R transaction:
SPRU976 – March 2006
Serial RapidIO (SRIO)
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