Texas Instruments TMS320C645X User Manual
Page 20
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1.25-3.125 Gbps
differential data
Rx Clock
recovery
S2P
10b
Clk 8b/10b
decode
8b
Clock
recovery
Rx
8b
8b/10b
decode
10b
Clk
S2P
Clock
recovery
Rx
8b
8b/10b
decode
10b
Clk
S2P
Clock
recovery
Rx
8b
8b/10b
decode
10b
Clk
S2P
PLL
Tx
Tx
Tx
Tx
P2S
P2S
P2S
P2S
8b
8b
8b
8b
10b
8b/10b
coding
Clk
8b/10b
coding
8b/10b
coding
8b/10b
coding
10b
Clk
10b
Clk
10b
Clk
FIFO
FIFO
FIFO
FIFO
System
clock
Capability
registers
Control
Command
and status
registers
SERDES
Clock domain 2
Clock domain 3
Clock domain 1
DMA
bus
Packet Generation
Lane striping
Lane de-skew
CRC error detection
CRC generation
Buf
fering address and data handof
f
FIFO
FIFO
FIFO
FIFO
SRIO Functional Description
Figure 4. SRIO Peripheral Block Diagram
Within the physical layer, the data next goes to the 8b/10b decode block. 8b/10b encoding is used by
RapidIO to ensure adequate data transitions for the clock recovery circuits. Here the 20% encoding
overhead is removed as the 10-bit data is decoded to the raw 8-bit data. At this point, the recovered byte
clock is still being used.
The next step is clock synchronization and data alignment. These functions are handled by the FIFO and
lane de-skewing blocks. The FIFO provides an elastic store mechanism used to hand off between the
recovered clock domains and a common system clock. After the FIFO, the four lanes are synchronized in
frequency and phase, whether 1X or 4X mode is being used. The FIFO is 8 words deep. The lane
de-skew is only meaningful in the 4X mode, where it aligns each channel’s word boundaries, such that the
resulting 32-bit word is correctly aligned.
The CRC error detection block keeps a running tally of the incoming data and computes the expected
CRC value for the 1X or 4X mode. The expected value is compared against the CRC value at the end of
the received packet.
After the packet reaches the logical layer, the packet fields are decoded and the payload is buffered.
Depending on the type of received packet, the packet routing is handled by functional blocks which control
the DMA access.
2.1.2
SRIO Packets
The SRIO data stream consists of data fields pertaining to the logical layer, the transport layer, and the
physical layer.
•
The logical layer consists of the header (defining the type of access) and the payload (if present).
•
The transport layer is partially dependent on the physical topology in the system, and consists of
source and destination IDs for the sending and receiving devices.
•
The physical layer is dependent on the physical interface (i.e., serial versus parallel RapidIO) and
includes priority, acknowledgment, and error checking fields.
2.1.2.1
Operation Sequence
SRIO transactions are based on request and response packets. Packets are the communication element
between endpoint devices in the system. A master or initiator generates a request packet which is
transmitted to a target. The target then generates a response packet back to the initiator to complete the
transaction.
20
Serial RapidIO (SRIO)
SPRU976 – March 2006