FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 62)

Release 1.0, 1 July 2002 F. Chapter A Instruction Definitions: SPARC64 V Extensions 51
Description The Floating-point Multiply-Add instructions multiply the registers specified by the
rs1 field times the registers specified by the rs2 field, add that product to the
registers specified by the rs3 field, then write the result into the registers specified
by the rd field.
The Floating-point Multiply-Subtract instructions multiply the registers specified by
the
rs1 field times the registers specified by the rs2 field, subtract from that
product the registers specified by the rs3 field, and then write the result into the
registers specified by the rd field.
The Floating-point Negative Multiply-Add instructions multiply the registers
specified by the
rs1 field times the registers specified by the rs2 field, negate the
product, subtract from that negated value the registers specified by the rs3 field, and
then write the result into the registers specified by the
rd field.
The Floating-point Negative Multiply-Subtract instructions multiply the registers
specified by the
rs1 field times the registers specified by the rs2 field, negate the
product, add that negated product to the registers specified by the rs3 field, and
then write the result into the registers specified by the rd field.
All of the operations above are treated as separate multiply and add/subtract
operations in SPARC64 V. That is, a multiply operation is first performed with a
complete rounding step (as if it were a single multiply operation), and then an add/
subtract operation is performed with a complete rounding step (as if it were a single
add/subtract operation). Consequently, at most two rounding errors can be
incurred.
1
Special behaviors in handling traps are generated in a Floating-point Multiply-Add/
Subtract instruction in SPARC64 V because of its implementation characteristics. If
any trapping exception is detected in the multiply part in the process of a Floating-
point Multiply-Add/Subtract instruction, the execution of the instruction is aborted,
the exception condition is recorded in
FSR.cexc and FSR.aexc , and the CPU traps
with the exception condition. The add/subtract part of the instruction is only
performed when the multiply-part of the instruction does not have any trapping
exceptions.
As described in the TABLE A-2 , if there are trapping IEEE754 exception conditions in
either of the operations FMUL or FADD/SUB , only the trapping exception condition is
recorded in the cexc , and the aexc is not modified. If there are no trapping IEEE754
exception conditions, every nontrapping exception condition is ORed into the cexc
and the cexc is accumulated into the aexc . The boundary conditions of an
unfinished_FPop trap for Floating-point Multiply-Add/Subtract instructions are
exactly same as for FMUL and FADD/SUB instructions; if either of the operations
1. Note that this implementation differs from previous SPARC64 implementations, which incurred at most one
rounding error.