FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 170)

Release 1.0, 1 July 2002 F. Chapter P Error Handling 159
The ERROR_MARK_ID (14 bits wide) identifies the error source. The hardware unit
that detects the error provides the error source_ID and sets the ERROR_MARK_ID
value.
The format of ERROR_MARK_ID <13:0> is defined in TABLE P-5 .
ERROR_MARK_ID Set by CPU
TABLE P-6 shows the ERROR_MARK_ID set by the CPU.
41:36 0 (6 bits).
35 Error bit. The value is unpredictable.
34:23 0 (12 bits).
22 Error bit. The value is unpredictable.
21:14 0 (8 bits).
13:0 ERROR_MARK_ID (14 bits).
ECC The pattern indicates 3-bit error in bits 63, 35, and 22, that is, the
pattern causing the 7F
16
syndrome.
TABLE P-5 ERROR_MARK_ID Bit Description
Bit Value
13:12 Module_ID: Indicates the type of error source hardware as follows:
00
2
: Memory system including DIMM
01
2
: Channel
10
2
: CPU
11
2
: Reserved
11:0 Source_ID: When Module_ID = 00
2
, the 12-bit Source_ID field is always set to 0.
Otherwise, the identification number of each Module type is set to Source ID.
TABLE P-6 ERROR_MARK_ID Set by CPU
Type of data with RAW UE Module_ID value (binary) Source_ID value
Incoming data from UPA 00
2
(Memory system) 0
Outgoing data to UPA ASI_EIDR <13:12>. 10
2
(CPU) is expected. ASI_EIDR (Identifier of self CPU)
U2 cache data, D1 cache data ASI_EIDR <13:12>. 10
2
(CPU) is expected. ASI_EIDR (Identifier of self CPU)
TABLE P-4 Format of Error-Marked Data
Data/ECC Bit Value