FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 147)

136 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
N.3 Interrupt Global Registers
Please refer to Section N.3. of Commonality.
N.4 Interrupt-Related ASR Registers
Please refer to Section N.4 of Commonality for details of these registers.
N.4.2 Interrupt Vector Dispatch Register
SPARC64 V ignores all 10 bits of VA <38:29> when the Interrupt Vector Dispatch
Register is written (impl. dep. #246).
N.4.3 Interrupt Vector Dispatch Status Register
In SPARC64 V, 32 BUSY/NACK pairs are implemented in the Interrupt Vector
Dispatch Status Register (impl. dep. #243).
N.4.5 Interrupt Vector Receive Register
SPARC64 V sets a 5-bit physical module ID ( MID ) value in the SID_L field of the
Interrupt Vector Receive Register. The SID_U field always reads as zero. SPARC64 V
obtains the interrupt source identifier SID_L from the UPA packet (impl. dep. #247).