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P.1.2 error_state transition error, P.1.3 urgent error, Error_state transition error 150 urgent error 150 – FUJITSU Implementation Supplement Fujitsu SPARC64 V User Manual

Page 161: Instruction-obstructing error

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SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

When the CPU detects the fatal error, the CPU enters FATAL

error_state

and

reports the fatal error occurrence to the system controller. The system controller
transfers the entire system state to the FATAL state and stops the system. After the
system stops, a FATAL reset, which is a type of power-on reset, will be issued to the
whole system.

P.1.2

error_state

Transition Error

An

error_state

transition error is a serious error that prevents the CPU from

reporting the error by generating a trap. However, any damage caused by the error
is limited to within the CPU.

When the CPU detects an

error_state

transition error, it enters

error_state

.

The CPU exits

error_state

by causing a watchdog reset, entering

RED_state

,

and starting instruction execution at the watchdog reset trap handler.

P.1.3

Urgent Error

An urgent error (

UGE

) is an error that requires immediate processing by privileged

software, which is reported by an error trap. The types of urgent errors are listed
below and then described in further detail.

Instruction-obstructing error

I_UGE

:

Instruction urgent error

IAE

:

Instruction access error

DAE

:

Data access error

Urgent error that is independent of the instruction execution

A_UGE

: Autonomous urgent error

Instruction-Obstructing Error

An instruction-obstructing error is one that is detected by instruction execution and
results in the instruction being unable to complete.

When the instruction-obstructing error is detected while

ASI_ERROR_CONTROL.WEAK_ED

= 0 (as set by privileged software for a normal

program execution environment), then an exception is generated to report the error.
This trap is nonmaskable.

Otherwise, when

ASI_ERROR_CONTROL.WEAK_ED

= 1, as with multiple errors or a

POST/OBP reset routine, one of the following actions occurs:

Whenever possible, the CPU writes an unpredictable value to the target of the
damaged instruction and the instruction ends.