FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 201)

190 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
P.9.2 Handling of an I1 Cache Data Error
I1 cache data is protected by parity attached to every doubleword.
When a parity error is detected in I1 cache data during an instruction fetch,
hardware executes the following sequence:
1. Reread the I1 cache line containing the parity error from the U2 cache.
The read data from U2 cache must contain only the doubleword without error or
the doubleword with the marked UE, because error marking is applied to U2
cache outgoing data.
2. For each doubleword read from U2 cache:
a. When the doubleword does not have a UE , save the correct data in the I1 cache
doubleword without parity error and supply the data for instruction fetch if
required.
There is no direct report to software for an I1 cache error corrected by refilling
data.
b. When the doubleword has a marked UE , set the parity bit in the I1 cache
doubleword to indicate a parity error and supply the parity error data for the
instruction fetch if required.
3. Treat a fetched instruction with an error as follows:
When the instruction with a parity error is fetched but not executed in any way
visible to software, the fetched instruction with the error is discarded.
Otherwise, fetch and execute the instruction with the indicated parity error.
When the execution of the instruction is complete, an
instruction_access_error
exception will be generated (precise trap), and the marked UE detection and its
ERROR_MARK_ID will be indicated in ASI_ISFSR .
P.9.3 Handling of a D1 Cache Data Error
D1 cache data is protected by 2-bit error detection and 1-bit error correction ECC,
attached to every doubleword.
Correctable Error in D1 Cache Data
When a correctable error is detected in D1 cache data, the data is corrected
automatically by hardware. There is no direct report to software for a D1 cache
correctable error.