FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 176)

Release 1.0, 1 July 2002 F. Chapter P Error Handling 165
■
Ideal specification (not implemented)
The
EE_OTHER bit is specified in ASI_STCHG_ERROR_INFO bit 14. When
hardware detects error_state transition errors other than those described
above, it sets ASI_STCHG_ERROR_INFO.EE_OTHER = 1.
P.4 Urgent Error
This section presents details about urgent errors: status monitoring, actions, and
end-methods.
P.4.1 URGENT ERROR STATUS ( ASI_UGESR )
The ASI_UGESR register contains the following information when an
async_data_error ( ADE ) exception is generated.
■
Detected I_UGE s and A_UGE s, and related information
■ The type of second error to cause multiple async_data_error traps
TABLE P-11 describes the fields of the ASI_UGESR register. In the table, the prefixes in
the name field have the following meaning:
■ IUG_ Instruction Urgent error
■ IAG_ Autonomous Urgent error
■ IAUG_ The error detected as both I_UGE and A_UGE
[1] Register name: ASI_URGENT_ERROR_STATUS
[2] ASI: 4C
16
[3] VA: 08
16
[4] Error checking: None
[5] Format & function: See TABLE P-11 .
[6] Initial value at reset: Hard POR: All fields are set to 0.
Other resets: The values of all
ASI_UGESR fields are
unchanged.
TABLE P-11 ASI_UGESR Bit Description (1 of 4)
Bit Name RW Description
Each bit in ASI_UGESR <22:8> indicates the occurrence of its corresponding error in a single- ADE trap as follows:
0: The error is not detected.
1: The error is detected.
Each bit in ASI_UGESR <22:16> indicates an error in a CPU register. The error detection conditions for these
errors are defined in Handling of Internal Register Errors on page 181.