FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 138)

Release 1.0, 1 July 2002 F. Chapter M Cache Organization 127
M.1.2 Level-1 Data Cache (L1D Cache)
The level-1 data cache is a writeback cache. Its characteristics are shown in
TABLE M-2 .
Although L1D cache is VIPT, TTE.CV is ineffective since SPARC64 V has unaliasing
features in hardware.
Data accesses bypass the L1D cache when they are noncacheable accesses.
Noncacheable accesses occur under one of three conditions:
■ The ASI used for the access is either ASI_PHYS_BYPASS_EC_WITH_E_BIT (15
16
)
or ASI_PHYS_BYPASS_EC_WITH_E_BIT_LITTLE (1D
16
).
■ DCUCR.DM = 0
■ TLB.CP = 0
Unlike the L1I cache, the L1D cache does not use MCNTL.NC_CACHE .
M.1.3 Level-2 Unified Cache (L2 Cache)
The level-2 unified cache is a writeback cache. Its characteristics are shown in
TABLE M-3 .
The L2 cache is bypassed when the access is noncacheable. MCNTL.NC_CACHE is not
used on the L2 cache.
TABLE M-2 L1D Cache Characteristics
Feature Value
Size 128 Kbytes
Associativity 2-way
Line Size 64-byte
Indexing Virtually indexed, physically tagged (VIPT)
Tag Protection Parity and duplicate
Data Protection ECC
TABLE M-3 L2 Cache Characteristics
Feature Value
Size 2 Mbytes
Associativity 2- or 4-way, in ASI_L2_CTRL (6A
16
)
Line Size 64-byte
Indexing Physically indexed, physically tagged (PIPT)
Tag Protection ECC
Data Protection ECC