FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 204)

Release 1.0, 1 July 2002 F. Chapter P Error Handling 193
doubleword and its ECC in the read data and those in the source U2 cache line are
changed to marked
UE data. The restrainable error ASI_AFSR.UE_RAW_L2$INSD is
detected.
Implementation Note – SPARC64 V detects ASI_AFSR.UE_FAW_L2$INSD only on
writeback.
P.9.5 Automatic Way Reduction of I1 Cache, D1 Cache, and
U2 Cache
When frequent errors occur in the I1, D1, or U2 cache, hardware automatically
detects that condition and reduces the way, maintaining cache consistency.
Way Reduction Condition
Hardware counts the sum of the following error occurrences for each way of each
cache:
■ For each way of the I1 cache:
■
Parity error in I1 cache tag or I1 cache tag copy
■
I1 cache data parity error
■ For each way of the D1 cache:
■
Parity error in D1 cache tag or D1 cache tag copy
■
Correctable error in D1 cache data
■
Raw UE in D1 cache data
■ For each way of U2 cache:
■
Correctable error and uncorrectable error in U2 cache tag
■
Correctable error in U2 cache data
■
Raw UE in U2 cache data
If an error count per unit of time for one way of a cache exceeds a predefined
threshold, hardware recognizes a cache way reduction condition and takes the
actions described below.
I1 Cache Way Reduction
When way reduction condition is recognized for the I1 cache way W (W = 0 or 1), the
following way reduction procedure is executed:
1. When only one way in I1 cache is active because of previous way reduction:
■
The CPU enters error_state .