FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 136)

F. A P P E N D I X
125
M
Cache Organization
This appendix describes SPARC64 V cache organization in the following sections:
■ Cache Types on page 125
■ Cache Coherency Protocols on page 128
■ Cache Control/Status Instructions on page 128
M.1 Cache Types
SPARC64 V has two levels of on-chip caches, with these characteristics:
■ Level-1 cache is split for instruction and data; level-2 cache is unified.
■ Level-1 caches are virtually indexed, physically tagged (VIPT), and level-2 caches
are physically indexed, physically tagged (PIPT).
■ All caches are 64 bytes in line size.
■
All lines in the level-1 caches are included in the level-2 cache.
■ Between level-1 caches, or level-1 and level-2 caches, coherency is maintained by
hardware. In other words,
■
eviction of a cache line from a level-2 cache causes flush-and-invalidation of all
level-1 caches, and
■
self-modification of an instruction stream modifies a level-1 data cache with
invalidation of a level-1 instruction cache.