FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 224)

F. A P P E N D I X
213
R
UPA Programmer ’s Model
This chapter describes the programmers model of the UPA interface of the
SPARC64 V. The registers for the UPA interface and the access method for those
registers are described. The appendix contains the following sections:
■ Mapping of the CPU’s UPA Port Slave Area on page 213
■ UPA PortID Register on page 214
■ UPA Config Register on page 215
R.1 Mapping of the CPU’s UPA Port Slave
Area
TABLE R-1 shows the mapping of the CPU’s UPA port slave area.
TABLE R-1 CPU’s UPA Port Slave Area Mapping
Relative Address
(Hex)
Length Possible Access Contents
0 0000 0000 8 Slave read from other
UPA port UPA PortID Register; defined in
Section R.2.
0 0000 0008
~ 1 FFFF FFFF -- None Nothing. Write is ignored and
undefined value is read.