Table f-3 – FUJITSU Implementation Supplement Fujitsu SPARC64 V User Manual
Page 104
Release 1.0, 1 July 2002
F. Chapter F
Memory Management Unit
93
F.10.4
I/D TLB Data In, Data Access, and Tag Read
Registers
IMPL. DEP. #234
:
The replacement algorithm of a TLB entry is implementation
dependent in JPS1.
TABLE F-3
MCNTL
Field Description
Bits
Field Name
RW
Description
Data <16>
NC_Cache
R/W
Force instruction caching. When set, the instruction lines fetched from a
noncacheable area are cached in the instruction cache. The
NC_Cache
has no effect on operand references. If
MCNTL.NC_Cache
= 1, the CPU
fetches a noncacheable line in four consecutive 16-byte fetches and stores
the entire 64 bytes in the I-Cache.
NC_Cache
is provided for use by
OBP
,
and
OBP
should clear the bit before exiting.
A write to
ASI_FLUSH_L1I
must be performed before
MCNTL.NC_CACHE
= 0 is set. Otherwise, noncacheable instructions may
remain on the L1 cache.
Data <15>
fw_fITLB
R/W
Force write to fITLB. This is the mITLB version of fTLB force write.
When
fw_fITLB
= 1, a TTE write to mITLB through ITLB Data In
Register is directed to fITLB.
fw_fITLB
is provided for use by
OBP
to
register the TTEs that map the address translations themselves into
fDTLB.
Data <13:12>
RMD
R
TLB RAM MODE. Handling of 4-Mbyte page entry is indicated on this
fileld.
00: 4-Mbyte page entry is stored in fully associative TLB.
01: reserved.
10: 4-Mbyte page entry is stored in 1024-entry, 2-way set associative
TLB.
11: 4-Mbyte page entry is stored in 512-entry, 2-way set associative
TLB.
This field is read-only. Writes to this field is ignored.
Data <14>
fw_fDTLB
R/W
Force write to fDTLB. When
fw_fDTLB
= 1, a TTE write to mDTLB
through DTLB Data In Register is directed to fDTLB.
fw_fDTLB
is
provided for use by
OBP
to register the TTEs that map the address
translations themselves into fDTLB.
Data <8>
JPS1_TSBP
R/W
TSB-pointer context-hashing enable. When
JPS1_TSBP
= 0, SPARC64 V
does not apply the context-ID hashing for 8-Kbyte or 64-Kbyte TSB
pointer generation. The pointer generation strategy is compatible with
UltraSPARC. When
JPS1_TSBP
= 1, SPARC64 V is in JPS1_TSBP mode,
meaning that the CPU applies the context-ID hashing to generate an 8-
Kbyte or 64-Kbyte page TSB pointer.