FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 225)

214 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
R.2 UPA PortID Register
The UPA PortID Register is a standard read-only register that accessible by a slave
read from another UPA port. This register is located at word address 00
16
in the slave
physical address of the UPA port. This register cannot be read or written by ASI
instructions.
The UPA PortID Register is illustrated below and described in TABLE R-2 .
FC
16
Reserved SREQ_S ECC Not
Valid
ONE_READ PINT_RDQ PREQ_DQ PREQ_RQ UPACAP Reserved
63 56 55 36 35 34 33 32 31 30 25 24 21 20 16 15 0
TABLE R-2 UPA PortID Register Fields
Bit Field Description
63:56 FC
16
Value = FC
16
55:36 — Reserved. Read as 0.
35 SREQ_S Encodes the SREQ outstanding size as a unit of four. Set to 1,
indicating maximum of four outstanding SREQ s.
34 ECC ECCNotValid. Signifies that this UPA port does not support ECC.
Set to 0.
33 ONE ONE_READ . Signifies that this UPA port supports only one
outstanding slave read P_REQ transaction at a time. Set to 0.
32:31 PINT_RDQ PINT_RDQ <1:0>. Encodes the size of the PINT_RQ and PINT_DQ
queues. Specifies the number of incoming P_INT_REQ requests
that the slave port can receive. Specifies the number of 64-byte
interrupt datums the UPA slave port can receive. Set to 1 since only
one interrupt transaction can be outstanding to
UPC at a time.
30:25 PREQ_DQ PREQ_DQ <5:0>. Encodes the size of PREQ_DQ queue. Specifies the
number of incoming quadwords the UPA slave port can receive in
its
P_REQ write data queue. Set to 0, since incoming slave data
writes are not supported by UPC .
24:21 PREQ_RQ PREQ_RQ <3:0>. Encodes the size of PREQ_RQ queue. Specifies the
number of incoming P_REQ transaction request packets the UPA
slave can receive. Set to 1, since only one incoming P_REQ to the
UPC can be outstanding at a time.