FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 196)

Release 1.0, 1 July 2002 F. Chapter P Error Handling 185
Error Type error_state error_state transition error.
(I) AUG_ xxxx The error is indicated by ASI_UGESR.IAUG_ xxxx = 1, and the error class is
autonomous urgent error.
I(A) UG_ xxxx The error is indicated by ASI_UGESR.IAUG_ xxxx = 1, and the error class is
instruction urgent error.
Not detected
(#dv) In SPARC64 V, the error is not detected. In the ideal specification, some
errors should be detected but this behavior is not implemented. See
SPARC64 V Implementation and the Ideal Specification on page 188.
COREERROR
(#dv)
In SPARC64 V, the ASI_UGESR.IUG_COREERR is detected. In the ideal
specification, other errors should be detected but this behavior is not
implemented. See SPARC64 V Implementation and the Ideal Specification on
page 188.
If an
LDXA instruction is used to load an ASI register and an
ASI_UGESR.IUG_COREERR error is detected, a trap will occur. If that happens
and IUG_COREERR is the only error indicated in ASI_UGESR , it is expected
that the trap handler will retry the LDXA instruction until the threshold of
urgent errors is exceeded on the processor.
Others The name of the bit set to 1 in ASI_UGESR indicates the error type.
Correction RED trap The whole register is updated and corrected when a RED_state trap occurs.
W The whole register is updated and corrected by use of an STXA instruction to
write the register.
W1AC The whole register is updated and corrected by use of an STXA instruction to
write 1 to the specified bit in the register.
WotherI The register is corrected by a full update of all of the following ASI registers:
• ASI_IMMU_TAG_ACCESS
• plus, when ASI_UGESR.IAUG_TSBCTXT = 1 is indicated in a single- ADE
trap: ASI_IMMU_TSB_BASE , ASI_IMMU_TSB_PEXT ,
ASI_PRIMARY_CONTEXT , ASI_SECONDARY_CONTEXT
WotherD The register is corrected by a full update of all of the following ASI registers:
• ASI_DMMU_TAG_ACCESS
• plus, when ASI_UGESR.IAUG_TSBCTXT = 1 is indicated in a single- ADE
trap: ASI_DMMU_TSB_BASE , ASI_DMMU_TSB_PEXT ,
ASI_DMMU_TSB_SEXT , ASI_PRIMARY_CONTEXT ,
ASI_SECONDARY_CONTEXT
DemapAll The error is corrected by the demap all operation for the TLB with the error.
Note that the demap all operation does not remove the locked TLB entry with
uncorrectable error.
Interrupt
receive The register is corrected when the UPA interrupt packet is received.
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Column Term Meaning