FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 137)

126 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
M.1.1 Level-1 Instruction Cache (L1I Cache)
TABLE M-1 shows the characteristics of a level-1 instruction cache.
Although an L1I cache is VIPT, TTE.CV is ineffective since SPARC64 V has
unaliasing features in hardware.
Instruction fetches bypass the L1I cache when they are noncacheable accesses.
Noncacheable accesses occur under one of three conditions:
■ PSTATE.RED = 1
■ DCUCR.IM = 0
■ TLB.CP = 0
When MCNTL.NC_CACHE = 1, SPARC64 V treats all instructions as cacheable,
regardless of the conditions listed above. See page 92 for details.
Programming Note – This feature is intended to be used by the OBP to facilitate
diagnostics procedures. When the OBP uses this feature, it must clear
MCNTL.NC_CACHE and invalidate all L1I data by ASI_FLUSH_L1I before it exits.
TABLE M-1 L1I Cache Characteristics
Feature Value
Size 128 Kbytes
Associativity 2-way
Line Size 64-byte
Indexing Virtually indexed, physically tagged (VIPT)
Tag Protection Parity and duplicate
Data Protection Parity