FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 40)

Release 1.0, 1 July 2002 F. Chapter 6 Instructions 29
Since size = 00 is not IMPDEP2B and since size = 11 assumed quad operations but
is not implemented in SPARC64 V, the instruction with size = 00 or 11 generates an
illegal_instruction exception in SPARC64 V.
6.3 Instruction Categories
SPARC V9 instructions comprise the categories listed below. All categories are
described in Section 6.3 of Commonality. Subsections in bold face are SPARC64 V
implementation dependencies.
■ Memory access
■
Memory synchronization
■ Integer arithmetic
■ Control transfer (CTI)
■ Conditional moves
■ Register window management
■
State register access
■ Privileged register access
■ Floating-point operate (FPop)
■ Implementation-dependent
6.3.3 Control-Transfer Instructions (CTIs)
These are the basic control-transfer instruction types:
■ Conditional branch ( Bicc , BPcc , BPr , FBfcc , FBPfcc )
■ Unconditional branch
■
Call and link ( CALL )
■ Jump and link ( JMPL , RETURN )
■
Return from trap ( DONE , RETRY )
■ Trap ( Tcc )
Instructions other than CALL and JMPL are described in their entirety in Section 6.3.2
of Commonality. SPARC64 V implements CALL and JMPL as described below.
CALL and JMPL Instructions
SPARC64 V writes all 64 bits of the PC into the destination register when
PSTATE.AM = 0. The upper 32 bits of r[15] ( CALL ) or of r[rd] ( JMPL ) are written
as zeroes when PSTATE.AM = 1 (impl. dep. #125).