Q.2.4 cache event counters, Cache event counters 208, I1 cache miss count (if_r_iu_req_mi_go) – FUJITSU Implementation Supplement Fujitsu SPARC64 V User Manual

Page 219: D1 cache miss count (op_r_iu_req_mi_go), I1 cache miss latency (if_wait_all), D1 cache miss latency (op_wait_all)

Text mode
Original mode

Q.2.4 cache event counters, Cache event counters 208, I1 cache miss count (if_r_iu_req_mi_go) | D1 cache miss count (op_r_iu_req_mi_go), I1 cache miss latency (if_wait_all), D1 cache miss latency (op_wait_all) | FUJITSU Implementation Supplement Fujitsu SPARC64 V User Manual | Page 219 / 255