Comtech EF Data SNM-1001L - Manual (Page 213)

11–1
Chapter 11. ASYMMETRICAL
LOOP TIMING
11.1 Asymmetrical Loop Timing
Asymmetrical Loop Timing is the same timing method that is designed into the
SDM-650B TROJAN interfaces. Refer to Figure 11-1 and Figure 11-2 for TX and RX
Asymmetrical Loop Timing block diagram. There are two advantages for using
Asymmetrical Loop Timing:
• Versatility: The user can select different transmit and receive data rates, yet still
clock the send data with the receive satellite clock.
• Fits easily into on site clocking schemes: The user may clock the send data with a
clock that is not necessarily operating at the same rate as the data rate.
The send timing may only be referenced from an external clock source that is equal to the
data rate in the basic modem.
The asymmetrical clock loop reference must be one of the following:
• Transmit terrestrial clock
• External clock input
• Receive clock input
Notes:
1. The clock inputs are as follows:
a. ≥ 64 kHz shall be divisible by 8 kHz.
b. ≥ 32 kHz but < 64 kHz shall be divisible by 600 Hz or 8 kHz.
c. < 32 kHz shall be divisible by 600 Hz.
2. The transmit clock source can be the same at the RX digital data rate or EXT
CLOCK if they are ± 100 PPM. This is provided on the basic unit, with or
without the asymmetrical loop timing option.